-- $Id: $
-- File name:   INTERCEPTOR
-- Created:     11/4/2010
-- Author:      Alyssa Welles
-- Lab Section: 337-04
-- Version:     1.0  Initial Design Entry
-- Description: The top level block of the system


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_UNSIGNED.ALL;
USE IEEE.std_logic_ARITH.ALL;

ENTITY INTERCEPTOR IS
	PORT(
		CLK : in std_logic;														--system clock
		RST_N : in std_logic;														--asynchronous system reset
		LOG : in std_logic;														--determines if in logging or output mode

		-- USB: Device-side I/O
		D_PLUS_DEVICE_IN : in std_logic;
		D_MINUS_DEVICE_IN : in std_logic;

		-- USB: Host-side I/O
		D_PLUS_HOST_OUT : out std_logic;
		D_MINUS_HOST_OUT : out std_logic;

		-- SRAM interface
		--MEMWAIT : in std_logic;
		S_DATA : inout std_logic_vector(7 downto 0);	 --data received from external memory block
		ADDR : out std_logic_vector(15 downto 0);			  --address line
		RE : out std_logic;
		WE : out std_logic
    );
END INTERCEPTOR;

ARCHITECTURE behav OF INTERCEPTOR IS
	signal D_PLUS_DEVICE_INTL : std_logic;
	signal D_MINUS_DEVICE_INTL : std_logic;
	signal D_PLUS_HOST_RX_INTL : std_logic;
	signal D_MINUS_HOST_RX_INTL : std_logic;

	signal R_DATA : std_logic_vector(7 downto 0);
	signal R_ERROR_RX : std_logic;
  signal RCVING_RX : std_logic;
	signal R_ENABLE : std_logic;
  signal EMPTY_RX : std_logic;

	signal W_ENABLE : std_logic;
	signal RCVING_TX : std_logic;
	signal R_ERROR_TX : std_logic;
	signal M_DATA : std_logic_vector(7 downto 0);
	signal FULL_TX : std_logic;

	signal DPLUS_M : std_logic;
	signal DMINUS_M : std_logic;
	
	signal EOP : std_logic;
	
	signal RE_INTL : std_logic;
	signal WE_INTL : std_logic;

	component USB_RCVR is
		port(
			CLK : in std_logic;
			RST_N : in std_logic;
			D_PLUS : in std_logic;
			D_MINUS : in std_logic;
			R_ENABLE : in std_logic;
			R_DATA : out std_logic_vector (7 downto 0);
			EMPTY : out std_logic;
			R_ERROR : out std_logic;
			RCVING : out std_logic
			-- Handshake bits?
		);
	end component;

	component MEM_CTL is
		port(
			CLK : in std_logic;
			RST_N : in std_logic;
			--R_ERROR_RX : in std_logic;
			LOG : in std_logic;
			RCVING : in std_logic;
			EMPTY : in std_logic;
			FULL : in std_logic;
			--MEMWAIT : in std_logic;
			R_ENABLE : out std_logic;
			W_ENABLE : out std_logic;
			--R_ERROR_TX : out std_logic;
			ADDR : out std_logic_vector(15 downto 0);
			WE : out std_logic;
			RE : out std_logic
		);
	end component;
	
	component MIU is
	  port(
	    NRE : in std_logic;
	    NWE : in std_logic;
	    MEMDATAREAD : out std_logic_vector(7 downto 0);
	    MEMDATAWRITE : in std_logic_vector(7 downto 0);
	    NWRITEENABLE : out std_logic;
	    NREADENABLE : out std_logic;
	    DATABUS : inout std_logic_vector(7 downto 0)
	  );
	end component;

	component TRANSMITTER is
		port(
			CLK : in std_logic;
			RST_N : in std_logic;
			LOG : in std_logic;
     		        M_DATA : in std_logic_vector(7 downto 0);
			R_ERROR : in std_logic;
			W_ENABLE : in std_logic;
			D_PLUS : out std_logic;
			D_MINUS : out std_logic;
			FULL : out std_logic
		);
	end component;
BEGIN
	URX: USB_RCVR port map(
		CLK => CLK,
		RST_N => RST_N,
		D_PLUS => D_PLUS_DEVICE_IN,
		D_MINUS => D_MINUS_DEVICE_IN,
		R_ENABLE => R_ENABLE,
		R_DATA => R_DATA,
		R_ERROR => R_ERROR_RX,
		RCVING => RCVING_RX
	);

	MEM: MEM_CTL port map(
		CLK => CLK,
		RST_N => RST_N,
		--R_ERROR_RX => R_ERROR_RX,
		LOG => LOG,
		RCVING => RCVING_RX,
		EMPTY => EMPTY_RX,
		FULL => FULL_TX,
		--MEMWAIT => MEMWAIT,
		R_ENABLE => R_ENABLE,
		W_ENABLE => W_ENABLE,
		--R_ERROR_TX => R_ERROR_TX,
		ADDR => ADDR,
		WE => WE_INTL,
		RE => RE_INTL
	);
	
	MIT: MIU port map(
	  NRE => RE_INTL,
	  NWE => WE_INTL,
	  MEMDATAREAD => M_DATA,
	  MEMDATAWRITE => R_DATA,
	  NREADENABLE => RE,
	  NWRITEENABLE => WE,
	  DATABUS => S_DATA
	);

	UTX: TRANSMITTER port map(
		CLK => CLK,
		RST_N => RST_N,
		LOG => LOG,
	        M_DATA => M_DATA,
		R_ERROR => R_ERROR_TX,
		W_ENABLE => W_ENABLE,
		D_PLUS => D_PLUS_HOST_OUT,
		D_MINUS => D_MINUS_HOST_OUT
	);
END behav;
